The main objective of this project is to design and implement a Verilog design of QPSK Digital Modulator based on the Xilinx FPGA. In recent years, Digital modulation has become less complex, more secure and more efficient in long distance transmission such as in satellite communication. Here, a 1Mbps QPSK modulator is designed for satellite communication applications. The input data generated using a PRBS generator and is then scrambled using a scrambler and a symbol mapper. The symbol mapper, maps the binary data to IQ symbols. A Root Raised Cosine filter is designed for interpolating the signals after which a CIC filter is used for interpolating the signals to the DAC sampling frequency. The DAC output is IQ modulated and up converted to an L band RF signal 1.2GHz . Thus, helping in long distance transmission. A basic receiver is built to test the transmission characteristics. This consists of a Root Raised Cosine RRC decimator, a Zero crossing detector and a descrambler. A channelizer is designed at the transmitter which simultaneously up converts a number of baseband signals to assemble a set of FDM channels in a single sampled data signal stream.
by Apoorva T R | Deepika Sankari G | Santhosh B "FPGA Implementation of QPSK Modulator and Transmit Channelizer for Satellite Communication"
Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-4 | Issue-5 , August 2020,
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