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To overcome these faults in the existing system a high-performance, fine grained streaming processor, known as a streaming accelerator element, is proposed which realizes accelerators as large-scale custom multi core networks. By implementing this approach with advanced program control and memory addressing capabilities, we can see that the program inefficiencies can be almost eliminated to enable performance and cost, which are not possible among other software-programmable solutions. When used to realize accelerators for matrix multiplication it is shown how the proposed architecture enables real-time performance. To support floating point operations we add Floating Point Unit (FPU) to the ALU of processing elements which performs IEEE 754 2008 single precision floating point operations addition, multiplication, and subtraction.
By Chinta Sravani | Dr. Prasad Janga | Mrs. S. SriBindu" Floating Point Operations Compatible Streaming Elements for FPGA Accelerators"
Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-5 , August 2018,
Paper URL: http://www.ijtsrd.com/papers/ijtsrd15853.pdf
Direct URL: http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/15853/floating-point-operations-compatible-streaming-elements-for-fpga-accelerators/chinta-sravani
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