In todays world, as the technology is developing so rapidly the designing of the systems are becoming more and more compact. In some systems even if the circuits are not compact; still there is a need of less power consumption. This brief introduces a mixed-logic design method for line decoders, combining transmission gate logic, pass transistor dual-value logic, and static complementary metal-oxide semiconductor (CMOS).
Two novel topologies are presented for the 2'“4 decoder: a 14-transistor topology aiming on minimizing transistor count and power dissipation and a 15-transistor topology aiming on high power-delay performance. Both normal and inverting decoders are implemented in each case, yielding a total of four new designs. Additionally, four new 4'“16 decoders are designed by using mixed-logic 2'“4 predecoders combined with standard CMOS postdecoder.
Low Power is a well established discipline; it has undergone lot of developments from transistor sizing, process shrinkage, voltage scaling, clock gating, etc., to adiabatic logic. This paper aims to elaborate on the recent trends in the low power design. This paper is the review of use of line decoder to reduce power consumption as well as reduce number of transistor and power dissipation.
By Priyanka M. Raut | Dr. R. M. Deshmukh""Low Power Mix Logic Design Using Line Decoder: A Review""
Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018,
URL: http://www.ijtsrd.com/papers/ijtsrd14146.pdf
Direct Link - http://www.ijtsrd.com/engineering/telecommunications/14146/low-power-mix-logic-design-using-line-decoder-a-review/ku-priyanka-m-raut
call for paper in ugc approved journals, international journal of science, open access journal of engineering
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